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Video Lecture Description Sub-Category Time Click to view video


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Mod-01 Lec-01 Introduction to Digital VLSI Design Flow VLSI Circuits 71 min Click to view videos
Mod-01 Lec-02 High Level Design Representation VLSI Circuits 58 min Click to view videos
Mod-01 Lec-03 Transformations for High Level Synthesis VLSI Circuits 58 min Click to view videos
Mod-02 Lec-01 Introduction to HLS: Scheduling, Allocation and Binding Problem VLSI Circuits 61 min Click to view videos
Mod-02 Lec-02 Scheduling Algorithms-1 VLSI Circuits 58 min Click to view videos
Mod-02 Lec-03 Scheduling Algorithms-2 VLSI Circuits 70 min Click to view videos
Mod-02 Lec-04 Binding and Allocation Algorithms VLSI Circuits 67 min Click to view videos
Mod-03 Lec-01 Two level Boolean Logic Synthesis-1 VLSI Circuits 68 min Click to view videos
Mod-03 Lec-02 Two level Boolean Logic Synthesis-2 VLSI Circuits 64 min Click to view videos
Mod-03 Lec-03 Two level Boolean Logic Synthesis-3 VLSI Circuits 84 min Click to view videos
Mod-03 Lec-04 Heuristic Minimization of Two-Level Circuits VLSI Circuits 77 min Click to view videos
Mod-03 Lec-05 Finite State Machine Synthesis VLSI Circuits 74 min Click to view videos
Mod-03 Lec-06 Multilevel Implementation VLSI Circuits 64 min Click to view videos
Mod-04 Lec-01 Introduction to formal methods for design verification VLSI Circuits 53 min Click to view videos
Mod-04 Lec-02 Temporal Logic: Introduction and Basic Operators VLSI Circuits 55 min Click to view videos
Mod-04 Lec-03 Syntax and Semantics of CTL VLSI Circuits 60 min Click to view videos
Mod-04 Lec-04 Syntax and Semantics of CTL -- Continued VLSI Circuits 69 min Click to view videos
Mod-04 Lec-05 Equivalence between CTL Formulas VLSI Circuits 61 min Click to view videos
Mod-05 Lec-01 Introduction to Model Checking VLSI Circuits 63 min Click to view videos
Mod-05 Lec-02 Model Checking Algorithms I VLSI Circuits 56 min Click to view videos
Mod-05 Lec-03 Model Checking Algorithms II VLSI Circuits 57 min Click to view videos
Mod-05 Lec-04 Model Checking with Fairness VLSI Circuits 57 min Click to view videos
Mod-06 Lec-01 Binary Decision Diagram: Introduction and construction VLSI Circuits 63 min Click to view videos
Mod-06 Lec-02 Ordered Binary Decision Diagram VLSI Circuits 62 min Click to view videos
Mod-06 Lec-03 Operation on Ordered Binary Decision Diagram VLSI Circuits 61 min Click to view videos
Mod-06 Lec-04 Ordered Binary Decision Diagram for State Transition Systems VLSI Circuits 61 min Click to view videos
Mod-06 Lec-05 Symbolic Model Checking VLSI Circuits 62 min Click to view videos
Mod-07 Lec-01 Introduction to Digital VLSI Testing VLSI Circuits 55 min Click to view videos
Mod-07 Lec-02 Functional and Structural Testing VLSI Circuits 60 min Click to view videos
Mod-07 Lec-03 Fault Equivalence VLSI Circuits 57 min Click to view videos
Mod-08 Lec-01 Fault Simulation-1 VLSI Circuits 52 min Click to view videos
Mod-08 Lec-02 Fault Simulation-2 VLSI Circuits 62 min Click to view videos
Mod-08 Lec-03 Fault Simulation-3 VLSI Circuits 68 min Click to view videos
Mod-08 Lec-04 Testability Measures (SCOAP) VLSI Circuits 60 min Click to view videos
Mod-09 Lec-01 Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras VLSI Circuits 55 min Click to view videos
Mod-09 Lec-02 D-Algorithm-1 VLSI Circuits 57 min Click to view videos
Mod-09 Lec-03 D-Algorithm-2 VLSI Circuits 66 min Click to view videos
Mod-10 Lec-01 ATPG for Synchronous Sequential Circuits VLSI Circuits 69 min Click to view videos
Mod-10 Lec-02 Scan Chain based Sequential Circuit Testing-1 VLSI Circuits 53 min Click to view videos
Mod-10 Lec-03 Scan Chain based Sequential Circuit Testing-2 VLSI Circuits 52 min Click to view videos
Mod-11 Lec-01 Built in Self Test-1 VLSI Circuits 60 min Click to view videos
Mod-11 Lec-02 Built in Self Test-2 VLSI Circuits 54 min Click to view videos
Mod-11 Lec-03 Memory Testing-1 VLSI Circuits 57 min Click to view videos
Mod-11 Lec-04 Memory Testing-2 VLSI Circuits 73 min Click to view videos

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